Short Information about DSP56301

For more details sie Motorola-User-Manual.

• DSP56300 Family Core
  • 66/80 MIPS with a 66/80 MHz internal clock at 3.0-3.6 volts
  • Single clock per instruction execution
  • Code compatible with DSP56000 family
  • Fully-static logic with operation to DC
  • Wait, stop and intelligent power control circuitry powers down unused memories, peripherals and core logic on each individual instruction.
  • OnCE with added JTAG support for system debugging and testing
  • On-chip PLL

ALU Enhancements over DSP56000

• Fully pipelined barrel shifter supports bit stream parsing and generation
• Conditional ALU instruction
• 16 bit arithmetic supports cellular and videotelephony standards

Address Generation Unit Enhancements over DSP56000

• 24 bit addressing provides 16M word addressing for Program, X and Y memories
• Program Counter relative addressing improves operating system and compiler efficiency
• Immediate offset addressing

Program Controller Enhancements over DSP56000

• Hard stack extension in data memory allows unlimited stack depth without programmer overhead
• Support for Instruction Cache

Direct Memory Access Unit

• 6 channel fully concurrent DMA supports 120 Mbyte/sec transfers at 80 MHz
• Dedicated address and data buses support concurrent memory accesses
• Supports peripheral interrupts, internal and external memory reads/writes